1. Field of the Invention
This invention relates generally to an apparatus for and method of channelling data into and between a group of registers in, for example, a calculator, and more particularly to such an apparatus and method in which data is automatically recirculated in a register whenever data is not being supplied thereto from another source.
2. Prior Art
Serial processors, and the like machines, employ interconnect logic for decoding and implementing instructions which are generated by a main control unit therein. Generally, the control unit generates such instuctions in response to an address supplied from an external source. Such an external source may include, for example, a keyboard or a macroinstruction storage register and address generator. The instructions generated by the control unit are employed for controlling the flow of data into and out of the storage registers, for controlling the transfer of data between such registers, and for controlling the recirculation of data in those registers.
It has been the practice in the past to design such interconnect logic such that it is dedicated to the particular processor in which it is to be employed. That is, such interconnect logic for a particular processor is designed especially for the particular instructions employed in that processor and the particular functions to be accomplished in the transmission of data into and out of the associated registers. This design philosophy promotes a number of distinct disadvantages which are discussed in greater detail in an application for U.S. Pat. Ser. No. 693,482, which is a continuation application of Ser. No. 584,637 now abandoned of Richard B. Simone, filed June 6, 1975. That application is referred to for a discussion of the problems encountered in the design and implementation of interconnect logic circuits employed in the past.
The invention disclosed in the above mentioned application employs a programmable logic array (PLA) as the interconnect logic between a main control unit and the data handling registers of a serial processor. The technique of employing a PLA as the interconnect logic and which is disclosed in that application for patent dictates that all of the inputs of the registers are connected to respective outputs of the PLA and all of the outputs of the registers are connected to respective inputs of the PLA. Accordingly, when the main control unit supplies instruction codes to appropriate inputs of the PLA, all of the data which will be supplied to the registers is supplied from or through the interconnect PLA. This is also true of any data which is to be recirculated in a particular register. That is, the output of the register in which data is to be recirculated is connected to an appropriate input of the PLA and is supplied therethrough in response to an appropriate command to another input of that PLA.
This technique of recirculating data in a register requires the use of a relatively large and expensive PLA, or the use of additional logic gates external to the PLA which are the equivalent of the logic contained in a PLA to perform the same function. It can be appreciated that a considerable savings in both hardware and, therefore, cost can be realized if such recirculation data need not be transmitted through such a PLA or the equivalent logic circuitry.